hi , i am Brian Page .

High Performance Computing Researcher,
and Software/Network Engineer

download resume

about me

I am a Professional Computer Science Engineering and Researcher specializing in High Performance Computing (HPC), hardware analysis, and software development.

As a seasoned high-performance computing (HPC) and advanced simulation researcher, I lead and participate in innovative modeling and simulation projects to identify and solve performance and scalability issues HPC will face in the future. Pioneered the first gate-level processor model in SST, assisted in the foundation the ModSim Tool Consortium for open-source tools, performed novel and emerging architecture characterization studies, and developed hardware specific algorithm implementations.

phone

+1 (240) 853-8806

email

brian@pagetechlabs.com

profile_image

education

2014 - 2016

Bachelor of Computer Science

California Polytechnic, Humboldt

Arcata, CA, USA

Minor in Applied Mathematics

2016 - 2019

Master of Computer Science and Engineering

University of Notre Dame

Notre Dame, IN, USA

Member of Upsilon Pi Epsilon

2019 - 2021

Doctor of computer science and Engineering

University of Notre Dame

Notre Dame, IN, USA

Thesis Topic: Scalability of Irregular Applications Member of Upsilon Pi Epsilon

skills

Programming Languages
C/C++

90%

Python

70%

Assembly

65%

html/CSS

90%

Javascript

90%

PHP

80%

Cilk/Cilk+

70%

CUDA

75%

SQL

70%

Parallel Computing & High Performance Computing (HPC)
Mutli-Threading

90%

OpenMP

85%

Partitioned Global Address Space (PGAS)

85%

POSIX Threads

85%

System Eval. & Characterization

80%

Multi-Processing

90%

Message Passing Interface (MPI)

85%

Remote Direct Memory Access (RDMA)

75%

Asynchronous Communication

70%

Performance Analysis & optimization

80%

Heterogeneous Computing

75%

Distributed Memory

80%

Shared Memory

80%

SHMEM / OpenSHMEM

70%

Custom Hardware Design and Evaluation
Logic Gates & Circuit Design

80%

FPGA

60%

Xilinx

65%

Vivado

60%

Hardware/Software Co-Design

75%

RISC-V

85%

Spike (RISC-V) Simulator

65%

Verilator

70%

Modeling & Simulation

85%

Structural Simulation Toolkit (SST)

90%

Gem5

80%

SPICE

45%

Scientific Computing and Data Analytics
Graph Analysis

80%

Knowledge Graphs

60%

Bi-Partite Matching

65%

Machine Learning

55%

Support Vector Machines (SVMs)

70%

Large Language Models (LLMs)

15%

PANDAS

25%

Containerization (Docker)

60%

Sparse Linear Algebra

75%

experience

  • 2024 - Present

    Science Applications International Corporation

    Goddard, MD, USA

    NASA Senior Software Engineer

    • Updated the Unified Atmospheric Algorithm (UAA) software within NASA’s Orbiting Carbon Observatory Science Software (OCSSW) suite to integrate new data extraction requirements in NetCDF files, facilitating advanced scientific processing.
    • Conduct performance analysis on scientific computing applications written in Python and C/C++ for the purpose of optimization at scale.

  • 2024 - Present

    PKB Research Labs, LLC

    Fort Mead, MD, USA

    Technical Director & HPC Engineer

    • Implemented the first-ever gate-level processor model in SST, a pipelined RISC-V design.
    • Developed ArionAI a domain specific GPT based generative AI model for computer architecture modeling and simulation.
    • Served as software engineering technical lead for reinforcement learning from human feedback (RLHF) projects seeking to improve accuracy and domain specificity of generative AI.

    2024 - Present

    PKB Research Labs, LLC

    Fort Meade, MD, USA

  • 2022 - Present

    National Security Agency (NSA)

    Maryland, USA

    High Performance Computing Researcher

    • Led the Modeling, Simulation, and Emulation team, managing day-to-day operations, setting strategic goals, and providing long-term vision. Proactively proposed new research topics and projects to drive innovation and team development.
    • Managed projects by defining scope and requirements, overseeing funding and budgets, and assessing productivity/risk.
    • Conducted High Performance Computing (HPC) scaling and performance research.
    • Investigated viability of RISC-V for HPC class systems.
    • Characterized and evaluated novel and emerging computer architectures including network interconnects, processing in memory (PIM), silicon photonics, and custom accelerator design.
    • Implemented the first-ever gate-level processor model in SST, a pipelined RISC-V design, using the custom ArchEssentials library.
    • Developed custom component libraries and models for the Structural Simulation Toolkit (SST).

  • 2021 - 2022

    Data Scientist - Postdoctoral Researcher

    Data Scientist - Postdoctoral Researcher

    • Implemented knowledge/property graph analytics.
    • Performance and scalability evaluations for heterogeneous distributed memory based HPC systems, like Sierra Systems.
    • Utilized the YGM asynchronous communication library to evaluate scalefree graphs on large scale HPC systems

    2021 - 2022

    Lawrence Livermore National Laboratory

    Livermore, CA

  • 2021 - 2021

    University of Notre Dame

    Notre Dame, IN, USA

    Postdoctoral Researcher

    • Conducted architectural design space exploration for performance optimization on novel systems.
    • Developed and evaluated high performance computing (HPC) applications.
    • Implemented hybrid applications with multi-processing and multi-threading, utilizing both distributed and shared memory with MPI and OpenMP.
    • Developed hardware-specific AI/ML algorithms employing communication avoidance and overhead mitigation techniques.
    • Emphasis on real time streaming and machine learning, on novel migratory thread architectures and execution.

  • 2019

    Visiting Student Scholar

    Visiting Student Scholar

    • Developed distributed and heterogeneous graph analytics.
    • Utilized the YGM asynchronous communication library to enable and optimize evaluation of astronomy data (big-data) for the purpose of identifying unique objects and identify their orbital paths. Terabytes of data across millions of individual files, requiring distributed computing via MPI.
    • Focus on higher order network (HONs) and temporal bi-partite matching using Sierra Supercomputing systems.

    2019

    Lawrence Livermore National Laboratory

    Livermore, CA USA

  • 2016 - 2021

    University of Notre Dame

    Notre Dame, IN, USA

    PhD Candidate - HPC Researcher

    • Conducted exploratory research into the scalability of irregular memory access (sparse data) applications.
    • Developed hybrid (shared+distributed memory) parallel software of sparse linear algebra.
    • Conducted performance analysis of HPC-class heterogeneous systems, incorporating GPUs and custom accelerators such as the Intel Xeon Phi Knights Landing.
    • Investigated novel implementations of SpMV and SpMM.
    • Implemented hybrid applications with multiprocessing and multi-threading, utilizing both distributed and shared memory with MPI and OpenMP.
    • Instructor of Record - Planned lectures, developed course materials, lectured on topics including multi-processing and multi-threading.

  • 2016

    National Science Foundation

    NTHU, Hsinchu, Taiwan

    Undergraduate Research Assistant on Design Automation

    • Investigated existing circuit classification techniques as well as developed multi-threaded clip feature classification tools to aid in similarity detection with reduced runtimes.

Publications

J. Li, J. D. Leidel, B. Page and Y. Chen, "Towards Cycle-accurate Simulation of xBGAS," 2024 International Conference on Computing, Networking and Communications (ICNC), Big Island, HI, USA, 2024, pp. 468-472, doi: 10.1109/ICNC59896.2024.10556078. read here


B. A. Page and P. Kogge, "The Evolution of a New Model of Computation," 2022 IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms (IA3), Dallas, TX, USA, 2022, pp. 9-18, doi: 10.1109/IA356718.2022.00008. read here


B. A. Page and P. M. Kogge, "Passel: Improved Scalability and Efficiency of Distributed SVM using a Cacheless PGAS Migrating Thread Architecture," 2021 12th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA), St. Louis, MN, USA, 2021, pp. 27-34, doi: 10.1109/ScalA54577.2021.00009. read here


B. A. Page and P. M. Kogge, "Greatly Accelerated Scaling of Streaming Problems with A Migrating Thread Architecture," 2021 IEEE/ACM 11th Workshop on Irregular Applications: Architectures and Algorithms (IA3), St. Louis, MO, USA, 2021, pp. 11-18, doi: 10.1109/IA354616.2021.00009. read here


B. A. Page and P. M. Kogge, "Deluge: Achieving Superior Efficiency, Throughput, and Scalability with Actor Based Streaming on Migrating Threads," 2021 IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, USA, 2021, pp. 1-6, doi: 10.1109/HPEC49654.2021.9622823. read here


Page,Brian A.; Kogge, Peter M., "Scalability of Hybrid SpMV with Hypergraph Partitioning and Vertex Delegation for Communication Avoidance,"International Conference on High Performance Computing & Simulation (HPCS 2020), Virtual, 2021. read here


Brian A. Page, Peter M. Kogge, "Scalability of streaming anomaly detection in an unbounded key space using migrating threads,"High Performance Computing: 36th International Conference, ISC High Performance 2021, Virtual Event, June 24–July 2, 2021, Proceedings 36, pp. 157-175, doi: 10.1007/978-3-030-78713-4_9. read here


Peter M. Kogge and Brian A. Page, "Locality: The 3rd wall and the need for innovation in parallel architectures," Architecture of Computing Systems: 34th International Conference, ARCS 2021, Virtual, June 7–8, 2021, Proceedings 34, pp. 3-18, doi: 10.1007/978-3-030-81682-7_1. read here


B. A. Page and P. M. Kogge, "Scalability of Streaming on Migrating Threads," 2020 IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, USA, 2020, pp. 1-8, doi: 10.1109/HPEC43674.2020.9286193. read here


B. A. Page and P. M. Kogge, "Scalability of Sparse Matrix Dense Vector Multiply (SpMV) on a Migrating Thread Architecture," 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), New Orleans, LA, USA, 2020, pp. 483-488, doi: 10.1109/IPDPSW50202.2020.00088. read here


B. A. Page and P. M. Kogge, "Scalability of Hybrid SpMV on Intel Xeon Phi Knights Landing," 2019 International Conference on High Performance Computing & Simulation (HPCS), Dublin, Ireland, 2019, pp. 348-357, doi: 10.1109/HPCS48598.2019.9188154. read here


P. M. Kogge, N. A. Butcher and B. A. Page, "Introducing Streaming into Linear Algebra-based Sparse Graph Algorithms," 2019 International Conference on High Performance Computing & Simulation (HPCS), Dublin, Ireland, 2019, pp. 486-495, doi: 10.1109/HPCS48598.2019.9188143. read here


B. A. Page and P. M. Kogge, "Scalability of Hybrid Sparse Matrix Dense Vector (SpMV) Multiplication," 2018 International Conference on High Performance Computing & Simulation (HPCS), Orleans, France, 2018, pp. 406-414, doi: 10.1109/HPCS.2018.00072. read here


Scott Burgess and Brian Page, "Cuda programming in the core curriculum: a preliminary study," Journal of Computing Sciences in Colleges, Vol 32, Issue 1, pp. 155-161, doi: 10.5555/3007225.3007256. read here

contact me

submit

Brian A. Page

High Performance Computing Researcher,
Software/Network Engineer

phone

+1 (240) 853-8806

email

brian@pagetechlabs.com